1. Field of the Invention
The present invention relates to a memory control apparatus for controlling a synchronous memory unit or a synchronous dynamic random access (SDRAM) unit.
2. Description of the Related Art
In an SDRAM unit, when an external address signal as well as a command signal such as a read command signal, a write command signal or a refresh command signal is supplied thereto, the external address signal is latched in a burst counter, and thereafter, the content of the burst counter is incremented by receiving a high speed clock signal, so that a burst of read, write or refresh operations are successively carried out in accordance with the incremented content of the burst counter. Therefore, if the clock signals of the SDRAM unit and a host such as a central processing unit (CPU) or a direct memory access (DMA) controller are in common, the read, write or refresh operations can be carried out with no loss of time, and the host can be operated with no wait time.
In a prior art data processing apparatus (see: JP-9-180438-A), a clock signal generator supplies source clock signals to a host, a memory control unit and an SDRAM unit, respectively.
The memory control unit receives an access request signal, an address signal and/or a data signal from the host to generate and transmit a clock enable signal, a command signal such as a read command signal, a write command signal or a refresh command signal, and/or a data signal to the SDRAM unit. As a result, an internal clock signal is generated within the SDRAM unit, so that a burst of read operations, write operations or refresh operations are successively carried out in accordance with the command signal and/or the data signal in synchronization with the internal clock signal. Thus, since the clock enable signal is activated by the access request signal and is inactivated by an idle state which has continued for a time period longer than a predetermined time period for ensuring an overhead, the power consumption of the SDRAM unit can be decreased. This will be explained later in detail.
In the above-described prior art data processing apparatus, however, since a stray capacitance associated with a connection between the clock signal generator and the SDRAM unit is always charged and discharged by the source clock signal, the power consumption dissipated in the above-mentioned stray capacitance is very large, which would increase the power consumption of the entire data processing apparatus.